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TPS23757
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SLVS948D – JULY 2009 – REVISED NOVEMBER 2013
ELECTRICAL CHARACTERISTICS – PoE AND CONTROL
[V DD = V DD1 ] or [V DD1 = RTN], V C = RTN, COM = RTN = ARTN, all voltages referred to V SS unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
DETECTION (DEN)
(V DD = V DD1 = RTN = V SUPPLY positive)
Measure I SUPPLY
Detection current
Detection bias current
V DD = 1.6 V
V DD = 10 V
V DD = 10 V, float DEN, measure I SUPPLY
62
399
64.3
406
5.6
66.5
414
10
μ A
μ A
V PD_DIS
Hotswap disable threshold
DEN leakage current
V DEN = V DD = 57 V, float V DD1 and RTN, measure I DEN
3
4
0.1
5
5
V
μ A
CLASSIFICATION (CLS)
(V DD = V DD1 = RTN = V SUPPLY positive)
13 V ≤ V DD ≤ 21 V, Measure I SUPPLY
R CLS = 1270 ?
1.8
2.1
2.4
I CLS
Classification current,
applies to both cycles
R CLS = 243 ?
R CLS = 137 ?
9.9
17.6
10.4
18.5
10.9
19.4
mA
R CLS = 90.9 ?
R CLS = 63.4 ?
26.5
38.0
27.7
39.7
29.3
42
Hysteresis
V CL_ON
V CL_H
V CU_OFF
V CU_H
Classification regulator lower
threshold
Classification regulator upper
threshold
Regulator turns on, V DD rising
Hysteresis (1)
Regulator turns off, V DD rising
(1)
11.2
1.55
21
0.5
11.9
1.65
22
0.75
12.6
1.75
23
1.0
V
V
Leakage current
PASS DEVICE (RTN)
V DD = 57 V, V CLS = 0 V, DEN = V SS , measure I CLS
(V DD1 = RTN)
1
μ A
On resistance
0.25
0.43
0.8
?
Current limit
Inrush limit
Foldback voltage threshold
V RTN = 1.5 V, V DD = 48 V, pulsed measurement
V RTN = 2 V, V DD : 0 V → 48 V, pulsed measurement
V DD rising
400
100
11
465
140
12.3
535
180
13.6
mA
mA
V
UVLO
UVLO_R
UVLO_H
UVLO threshold
V DD rising
Hysteresis (1)
33.9
4.4
35
4.55
36.1
4.76
V
APb
V C = 12 V, float V DD1 , V DD = 48 V, ARTN = V SS
ON characteristic
Leakage current
V APD = 2 V, CTL = ARTN, (V APb - V ARTN ) = 0.6 V
V APb = 18 V, (V APD -V ARTN ) = 0 V, (V PPD - V VSS ) = 0 V
2
10
mA
μ A
t APb
Delay
From start of switching to APb active
5
9
15
ms
THERMAL SHUTDOWN
Turnoff temperature
T J rising
135
145
155
°C
Hysteresis (2)
20
°C
(1)
(2)
The hysteresis tolerance tracks the rising threshold for a given device.
These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product
warranty.
hi
50%
lo
hi
50%
lo
t DT1
t DT2
time
Figure 2. GATE and GAT2 Timing and Phasing
Copyright ? 2009–2013, Texas Instruments Incorporated
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